1. Field of the Invention
The present invention relates to techniques for handling multi-access instructions in a data processing apparatus, and more particularly to techniques for handling a multi-access instruction of the type that when executed causes both an access request of a first type and an access request of a second type to be generated, the multi-access instruction requiring that the accesses specified by those two access requests are made without any intervening accesses taking place.
2. Description of the Prior Art
When a processor is executing instructions, this may result in the generation of access requests specifying accesses to one or more slave devices. These slave devices are typically coupled to the processor via one or more interface units, with the access requests being passed to the appropriate interface unit for processing.
In a typical implementation, each interface unit would have an associated bus for communicating with the various slave devices, and an arbitration unit would be used to arbitrate between the various accesses being made by the interface units to ensure that only one interface unit has access to any particular slave device at any one time.
In a typical prior art implementation, one interface unit (also referred to herein as a master logic unit) would be responsible for processing access requests of both the first type and the second type, and hence upon execution of the particular type of multi-access instruction mentioned above, the access requests specified by that multi-access instruction would be routed to a single interface unit for execution. An example of such a multi-access instruction is a swap instruction, in this instance the access request of the first type being a read access request, the access request of the second type being a write access request, and the relevant slave device being a storage device such as a memory, an external register, a FIFO buffer, etc. The swap instruction specifies a read access request used to read data from an access address of the slave device into a first register of the data processing apparatus, followed by a write access request used to write data from a second register of the data processing apparatus into the access address of the slave device. The swap instruction requires that both the read access and the write access be made to the slave device without any intervening accesses to the slave device taking place.
In a typical prior art implementation, this can readily be achieved, since there would typically be a single read and write interface unit which is able to issue an appropriate locking signal to the arbitration unit to ensure that once it has been given access to the slave device, it can maintain sole access to the slave device whilst issuing both the read and the write access.
However, it is becoming desirable to increase the number of interface units, each being provided with their own bus for accessing the slave devices, so as to increase the bandwidth available for processing access requests, thus enabling an increase in performance, and increased flexibility. As an example, it is becoming desirable to provide within a data processing apparatus a separate data read interface and a separate data write interface, each provided with a separate bus for connection to the various slave devices. A segmented memory, for example, can then be considered as multiple slave devices, with this architecture allowing a read to one segment to occur via the read interface unit whilst simultaneously a write from another segment of the memory is occurring via the write interface. It will be appreciated that such an approach significantly increases the flexibility with which access requests can be processed, and can further yield significant performance benefits.
However, for multi-access requests of the above described type, for example a swap instruction, such an architecture presents a problem. Considering the example of the swap instruction, it can be seen that with the above architecture the read access request of the swap instruction would be issued to the read interface unit, whilst the write access request of the swap instruction would be issued to the write interface unit. Since the read and the write interface units use different buses for accessing the slave device (e.g. a memory), the read interface unit will need to release its lock signal after it has issued the read access request, in order that the write interface unit can then request access to the slave device to process the write access request. Since the swap instruction involves a read from a particular access address and then a write to that same access address, it is clear that the same slave device (e.g. the same memory segment) needs to be accessed by both interface units. This presents a problem, since it can no longer be ensured that an intervening access to that slave device will not occur between the read interface unit releasing its lock signal and the write interface unit gaining access to the slave device in order to process the write access request.
Accordingly, it would be desirable to provide a technique which enabled a first master logic unit to be provided to process access requests of a first type and a second master logic unit to be provided to process access requests of a second type, but which still enabled a multi-access instruction to be executed which required a first type access request and a second type access request to be processed without any intervening accesses taking place.